Hardware Acceleration of SIKE on Low-End FPGAs

Abstract

In this letter, we present the design and implementation results of two hardware accelerators for the supersingular isogeny key encapsulation (SIKE) suite. These designs aim at enabling quantum-safe cryptography solutions for constrained platforms by offloading the cost of bulk arithmetic from the main processor. One of the proposed architectures has area reduction as the main implementation goal; the second design improves the former on the energy footprint. This software–hardware co-design addresses the challenges of performing bulk arithmetic in software and reducing the control complexity in hardware, thus minimizing the communication overheads found on simple arithmetic accelerators. Compared to other designs in the literature, the proposed architectures do not rely on in-fabric memory and processing units, a key point for porting such solutions to any implementation technology such as field-programmable gate arrays (FPGAs).